80386 Microprocessor :
Software Model, memory address space, data organisation, data types, registers
and memory segmentation in the real address mode, real mode instructions. Real
80386 Protected Virtual Address Mode :
Register model, memory management, address translation, segmentation and segment
descriptor table, segment selectors and descriptors, protection model, data
access and control transfer, Multi tasking, task state segment and task
switches. I / O level protection , paging, protected mode interrupts and
exceptions. their priorities, and interrupt / exception transfer methods.
Virtual 86 mode of operation. Protected mode specific instructions.
80386 signal interface :
Bus states, pipelined and non pipelined bus cycles, memory and I/O
interfaces, cache memory concepts, cache architectures, Direct mapped,
two way set associative cache, cache coherency, Typical cache controller and its
operating system concepts. Virtual memory concepts, single tasking and multi
tasking concepts, requirements of protection in multitasking applications. Usage
in a cache memory subsystem.
The Industry Standard bus Architecture : Introduction to 8 and 16 bit transfers. ISA interrupt subsystem, 82C59A usage and cascading of two 82C59A devices, The IRQ-2 redirect, shareable interrupts, NMI, DMA review, DMA transfer modes of the 8237A controller, ISA DMA subsystem, DMA bus cycle, DMAC addressing capability, addressing local bus memory, ISA bus master capability, bus masters and DRAM refresh. The ISA real time clock and configuration RAM, ISA timer.
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